FAB INTELLIGENCE DOSSIER
Malta, NY · 300mm FD-SOI / RF / automotive · Generated 26 May 2026
Process / wafer size
300mm FinFET, 22FDX FD-SOI, RF SOI, SiPh
CHIPS exposure
$1.587B federal + $575M NY State; capacity to triple over 10 yrs
Signal strength
Active ramp — Apple/Cirrus Logic AMP partner (Mar 2026)
Headcount on site
~2,000 manufacturing; ~1,200 engineering
| Parent | GlobalFoundries Inc. (Nasdaq: GFS), HQ in Malta, NY |
| Site role | GF's most advanced U.S. fab; 300mm leading-edge 300mm facility known internally as Fab 8 |
| Process specialties | 300mm FinFET (14/12nm), 22FDX FD-SOI, RF-SOI, silicon photonics, automotive-grade analog |
| End markets | Automotive (GM, Renesas), smart mobile (Apple/Cirrus Logic), aerospace & defense, data center / CPO |
| Current capacity | ~400,000 300mm wafers/year today; expected to triple over 10+ years under CHIPS expansion |
| Status (May 2026) | Active CHIPS-funded buildout: existing-fab capability expansion + new 358,000 sq ft fab + new packaging/test center |
Apple/Cirrus Logic AMP partnership puts a new silicon process at Malta
Mar 2026On March 26, 2026 Apple announced that it is working with Cirrus Logic and GlobalFoundries to establish new semiconductor process technologies at GlobalFoundries' facility in Malta, New York. GlobalFoundries' newest silicon process will be available in the U.S. for the first time to enable key technologies for Apple products, and the collaboration enables Cirrus Logic to develop mixed-signal solutions including advanced ICs to power Face ID systems. This is a brand-new process node coming up at Fab 8 with a marquee customer attached — exactly the moment when inspection criteria, defect Paretos and classifier definitions are still being authored.
Q1 FY26 earnings: Malta tape-outs cited as proof of onshoring traction
May 2026On the May 5, 2026 Q1 FY26 call, CEO Tim Breen explicitly tied design-win momentum to Malta. Per the transcript: 'we continue to see a meaningful increase in customer engagements and design win activity specifically linked to onshoring. For example, last month, Apple announced a joint collaboration with Cirrus Logic and GF to bring new process technologies to our Malta, N.Y.' Separately Breen highlighted 'new tape-outs in Malta, New York, for a pair of CPO design wins' on the silicon photonics SCALE platform. GF also reported first-quarter 2026 revenue of $1.6 billion, down 11% from Q4 2025 and up 3.1% year over year, with about 579,000 300-millimeter-equivalent wafers shipped, up 7% from the prior-year period — Malta is carrying mix.
Final CHIPS Act award funds a new Malta fab + capability expansion
Nov 2024Per NIST's CHIPS office, the U.S. Department of Commerce awarded GlobalFoundries up to $1.587 billion in direct funding under the CHIPS and Science Act to support the company's capital investment of approximately $14 billion over the next 10-plus years in its U.S. manufacturing sites in New York and Vermont. The investment includes a new state-of-the-art facility in New York, the capability and capacity expansion of an existing facility in New York, and the modernization of the company's operations in Vermont. The Malta scope is three discrete projects: a new large-scale 300mm fab expected to produce high-value technologies not currently available in the United States, a capacity expansion for advanced packaging with a focus on silicon photonics that would enable a fully integrated pureplay foundry wafer manufacturing and advanced packaging process flow in the U.S. for the first time, and a capacity expansion of GF's existing Malta fabrication facility to secure a dedicated supply of essential semiconductor technologies. Disbursement is milestone-based.
Open Malta reqs explicitly ask for ML/data tooling on yield and defect work
Aug 2025GF's own listings on the 2026 NCG track describe the Malta yield function as driving yield improvement, process optimization, and defect reduction in advanced nodes; monitoring and analyzing semiconductor process and yield data to identify trends, anomalies, and opportunities for improvement; collaborating with Process, Equipment, Defect Engineering, and Product Engineering teams to resolve yield and performance issues; supporting process development and integration for new technology nodes; conducting root cause analysis using statistical tools and data mining; and developing and implementing DOE to optimize process conditions and improve yield. The same posting asks for experience in data automation and scripting with Python, R, SQL or JMP/JSL . A separate Indeed snapshot for Malta lists Process Engineer - Defect Engineering (Silicon Photonics) as an open req. This is the in-house tooling line — defect classification work is being asked of newly hired engineers, not bought from a vendor.
NY State adds $575M for new Malta advanced packaging / test center
Jan 2025New York is ushering in a massive manufacturing hub. Gov. Kathy Hochul says GlobalFoundries will invest $575 million to create a new packaging and testing center at its Malta facility. GlobalFoundries manufactures semiconductor chips used in various technologies. Hochul says this will help bolster national security and drive economic growth in New York. This is on top of the federal CHIPS award and stands up the advanced-packaging leg of the Malta campus — a process surface (post-bond, post-CMP, photonics bump) where defect classification recipes are typically reauthored on every tool generation.
Senior Vice President & General Manager, New York Fab (Malta / Fab 8)
23+ yrs at GF/Chartered. Started as a lithography process development engineer in Singapore, ran Malta's litho module, then VP of manufacturing engineering before stepping up to GM in May 2023. Owns the Malta P&L and the CHIPS ramp.
Senior Member of Technical Staff — Integration and Yield, GlobalFoundries
Long-tenured integration/yield engineer with a publication trail on defect-detection methodology — including Puma double dark-field wafer inspection for micro-masking defects in 32nm HKMG SOI gate module and segmented auto-thresholding for BEOL CMP defectivity. This is the engineer who lives in the inspection-recipe-tuning layer.
Vijayalakshmi Seshachalam
CVD Process Engineer Lead, GlobalFoundries (ASMC 2024 conference co-chair)
Co-chaired the SEMI Advanced Semiconductor Manufacturing Conference in 2024 — a forum whose technical track includes defect inspection & reduction, yield enhancement, and big-data / ML for fab data. Conference-track visibility means she sees vendor pitches across the inspection ecosystem.
+ 12 more identified · full list in export
Standing up inspection logic for a brand-new silicon process under Apple / Cirrus Logic
Confidence: highApple's March 2026 AMP announcement explicitly states GlobalFoundries' newest silicon process will be available in the U.S. for the first time to enable key technologies for Apple products. A first-of-its-kind U.S. process at Malta means the defect Pareto, the nuisance-filter thresholds, and the SEM/optical classifier categories are being authored from scratch in parallel with the customer's risk lots. CEO Tim Breen confirmed on the May 5 2026 earnings call that the Malta tape-outs are already cited as proof of onshoring traction, so the schedule pressure on the inspection team is real.
SIXSENSE ANGLE
No-code defect classifier trained per fab on Malta's own SEM and optical images — lets the integration and defect-engineering team author, tune and version inspection criteria during the ramp instead of waiting on a tool-vendor retraining cycle.
Inspection recipes have to span fab + advanced packaging + silicon photonics on one campus
Confidence: highThe NIST CHIPS award funds three Malta projects in parallel: a new state-of-the-art 300mm fab, a capacity expansion for advanced packaging with a focus on silicon photonics that would enable a fully integrated pureplay foundry wafer manufacturing and advanced packaging process flow in the U.S. for the first time, and a capacity expansion of the existing Malta fab for essential automotive technologies. The same defect-engineering team now owns inspection logic across wafer-level FEOL/BEOL, photonics, and bump/post-bond surfaces — a process-agnostic classification problem rather than a single-tool one.
SIXSENSE ANGLE
Process-agnostic classifier footprint — same authoring environment from 300mm logic wafer to silicon photonics interposer to advanced-package bump, so the Malta defect team isn't running three disconnected vendor stacks for three CHIPS-funded process surfaces.
Malta is hiring the yield/defect work in-house, not outsourcing it to a tool vendor
Confidence: highThe 2026 NCG req for Process Integration & Yield at Malta describes the role as driving yield improvement, process optimization, and defect reduction in advanced nodes; collaborating with Process, Equipment, Defect Engineering, and Product Engineering teams to resolve yield and performance issues; and conducting root cause analysis using statistical tools and data mining techniques with data automation and scripting with Python, R, SQL or JMP/JSL called out. A separate Malta listing names Process Engineer - Defect Engineering (Silicon Photonics) . GF is staffing engineers who write classification logic themselves — the buyer for a no-code authoring layer rather than a black-box appliance.
SIXSENSE ANGLE
Configurable inspection logic that engineers (yield, process integration, defect metrology) tune themselves — fits the in-house data/JMP/Python workflow the Malta team is already hiring for, instead of asking them to file a vendor ticket every time the recipe needs to move.
Automotive-grade defect-density discipline on a ramping mix
Confidence: mediumSenator Schumer described Malta's CHIPS mandate as funding especially for the feature-rich, legacy chips that GlobalFoundries produces in Malta and that are essential for America's auto industry and national defense. The CHIPS scope also adds critical technologies already in production at GF's Singapore and Germany facilities, to enable a secure and reliable supply of domestically manufactured essential chips for the U.S. auto industry. Cross-fab technology transfer typically reopens the defect Pareto — Singapore/Dresden inspection recipes don't drop in unchanged onto Malta toolsets — and automotive customers (GM, Renesas) hold tighter ppm targets than mobile.
SIXSENSE ANGLE
Closed-loop yield feedback tying defect classifications to specific process / tool / chamber / lot signals — turns a cross-fab tech-transfer ramp into a days-not-quarters feedback cycle on the automotive defect modes that move ppm.
Open with Andrew Stamper, not Hui Peng Koh. Koh runs the site P&L and is the eventual exec sponsor, but the conversation that actually goes anywhere starts inside the inspection-recipe layer. Stamper is an SMTS on the Integration and Yield team whose public publication trail at GF is squarely on what SixSense touches: Puma double dark-field inspection recipes for micro-masking defects in HKMG SOI gate, In-line Defect Organizer (iDO) classification of CMP scratches, and segmented auto-thresholding for BEOL Cu CMP defectivity. That's the exact authoring surface — engineer-tunable classification logic on real fab images — where SixSense replaces a vendor cycle.
Lead with a specific question, not a capability pitch. The Apple/Cirrus Logic AMP announcement on March 26, 2026 confirmed that Malta is standing up a process node that has never run in the U.S. before, with a marquee customer's risk lots attached. The natural peer question to Stamper is whether his team is authoring the new classifier per defect mode on the SEM side or staying on optical / Puma-class dark-field for early ramp, and how they're handling the nuisance-defect rate before the Pareto stabilizes. That's a question only somebody who's read his earlier work would ask.
The timing window is now. The Q1 FY26 call (May 5, 2026) confirmed Malta tape-outs are already happening for the new process and for the CPO design wins on SCALE. The packaging/test center buildout from the $575M January 2025 NY State commitment is in parallel. Once the first risk-lot Pareto stabilizes, the inspection-logic decisions are locked in for the rest of the ramp — getting in before that lock-in is the difference between being the tool the engineers reach for and being the tool the vendor team evaluates next year.
DRAFT EMAIL TO ANDREW STAMPER
SubjectDefect-classifier authoring at Malta ahead of the new Apple/Cirrus process ramp
Andrew — re-read your earlier work on Puma 9550 dark-field recipe tuning for micro-masking defects in the HKMG SOI gate module, and your segmented auto-thresholding approach for BEOL Cu CMP — both still some of the clearest writeups I've seen on what engineer-authored classification recipes actually look like in production. Reason I'm reaching out: with the Apple / Cirrus Logic AMP collaboration putting a brand-new U.S. silicon process at Malta (announced March 26), plus the SCALE CPO tape-outs Tim Breen called out on the Q1 call, I'm guessing your integration-and-yield team is authoring a fresh defect Pareto and a new classifier set in parallel with the first risk lots. Curious whether you're standing the early-ramp classifier up on the SEM side or staying on optical / dark-field while the nuisance rate settles — and where the bottleneck is sitting right now, recipe authoring vs. SEM review throughput vs. tying classifications back to the chamber/lot signals. I work with fab engineering teams on the layer where yield and defect-metrology engineers author and tune classification logic themselves (no-code, on the fab's own SEM/optical images), so the engineer who owns the recipe doesn't have to file a vendor ticket every time the inspection criteria move during a ramp. Not a pitch — happy to share a short writeup on how a couple of other 300mm fabs cut classifier-iteration time during a new-process ramp, and would genuinely like your read on whether the binding constraint at Malta right now is on the authoring side or on closing the loop back to process/tool data. Worth a 20-minute call in the next two weeks? [Your name]