FAB INTELLIGENCE DOSSIER
Boise, ID · 300mm DRAM (1γ / 1δ) · Generated 26 May 2026
Process
300mm DRAM, EUV 1γ → 1δ
CHIPS exposure
$6.165B award + $1.2B redirected from Clay
Signal strength
Hot — ramp accelerated, sold-out HBM4 backlog
First wafers
ID1 DRAM output H2 CY2027; construction complete 2026
| Parent | Micron Technology Inc. (NASDAQ: MU), HQ Boise ID |
| Site | Fab ID1, co-located with Micron's Boise R&D Center of Excellence |
| Process | Leading-edge DRAM (1γ ramping, 1δ in development with next-gen EUV) |
| Cleanroom | ~600,000 sq ft per fab; two HVM fabs planned (ID1 + ID2) |
| End markets | Data center DRAM (DDR5, LP5), HBM4 base/core dies for NVIDIA Vera Rubin |
| Status | Construction completing 2026; first wafer output 2H CY2027; ID2 accelerated via $1.2B CHIPS re-allocation from Clay NY |
| Funding | Up to $6.165B CHIPS direct funding (Dec 2024) + AMIC investment tax credit eligibility |
| Workforce target | ~3,500 direct Micron hires plus OEM (Lam, TEL, ASML, AMAT) field engineers across both Idaho fabs |
1γ DRAM declared 'fastest ramp to mature yields' in company history — and is the gating bit driver into HBM4
Mar 2026In Micron's Q2 FY26 prepared remarks (18 Mar 2026), management stated: 'Our 1γ node was already the fastest ramp to mature yields, is ramping volumes faster than all prior nodes in our history and is on track to become a majority of our DRAM bit mix by mid-calendar 2026.' On the same call Sanjay Mehrotra committed to 'increase EUV adoption at the 1δ (1-delta) DRAM node utilizing the latest-generation EUV tools' and tied Boise directly to time-to-market: 'we expect colocation of R&D and high-volume manufacturing at our Boise and our Singapore sites to speed up time to market for our leading-edge products.' Any yield regression on 1γ has direct knock-on to HBM4 12-Hi / 16-Hi yields, which Micron has already pre-sold for calendar 2026.
Micron reallocated ~$1.2B of CHIPS funding from Clay NY to accelerate Boise ID1/ID2
Nov 2025Per the Clay project's final environmental impact report (Nov 2025), Micron amended its $6.1B CHIPS Act agreement to shift approximately $1.2B from the New York project to the Boise site, pulling ID2 forward of Clay Fab 1 (now slipping to 2030). Construction Dive: 'The tech company redirected about $1.2 billion in federal support from New York to its ID2 fab in Boise, Idaho.' This makes Idaho the de-facto priority US ramp site and tightens the schedule pressure on first-silicon yield at ID1.
Active hiring spike: RDA (Realtime Defect Analysis) and Product Yield Analytics roles at Boise, ML/ML-vision explicitly required
Jan 2026Two requisition families are open at the Boise site as of early 2026. (1) 'RDA Engineer, DRAM' (posted Jan 13, 2026) and 'New College Grad — RAM RDA Process Engineer ID1' (Jan 16, 2026): 'use state-of-the-art defect detection equipment and processes to troubleshoot and solve inline defect and process issues … run a team to reduce inline defectivity … ensure RDA has inline visibility to defects to prevent excursion.' (2) 'Product Yield Analysis and Analytics Engineer — TPG' (JR65374): scope is 'developing and enhancing our current software ecosystem for defect analysis … leveraging your expertise in data analytics, software development, machine learning, and engineering problem-solving to build tools that identify defects impacting yield and quality.' The 'Intern — RDA Yield Technology' posting explicitly calls for 'machine learning and machine vision techniques to improve defect analysis.' Micron is staffing the in-house defect-classification organization for the ID1 ramp right now.
PSMC Tongluo (P5) 300mm fab acquisition — Boise yield/methods will travel to a new HVM site by H2 2027
Jan 2026On 17 Jan 2026 Micron signed an exclusive LOI to acquire PSMC's P5 fab (Tongluo, Taiwan) — 300,000 sq ft of 300mm cleanroom — for $1.8B, closing by Q2 2026 and contributing 'meaningful DRAM wafer output beginning in the second half of calendar 2027.' EVP Global Ops Manish Bhatia framed the deal as a capacity grab in a market 'where demand continues to outpace supply.' Practically, this means the same yield-methods organization that owns Boise's 1γ ramp will simultaneously qualify a brownfield 300mm site on a 12–18 month clock — multiplying the demand for tooling that doesn't require months of vendor-built classifier re-training.
Q1 FY26 call: 1γ named as 'primary driver of DRAM bit growth in calendar 2026' — Boise R&D explicitly coupled to transition
Dec 2025In the 17 Dec 2025 prepared remarks, Mehrotra stated: '1-gamma will be the primary driver of our DRAM bit growth in calendar 2026 and will be the majority of our bit output in the second half of the calendar year' and explicitly: 'We are enabling future DRAM technology transition in coordination with our Boise R&D team.' Futurum confirmed FY26 capex was raised from $18B to $20B, 'prioritizing HBM capacity and 1-gamma output.' Boise R&D output gates the entire Micron DRAM roadmap through CY2027.
Corporate Vice President, Front End U.S. Expansion (Boise)
Boise-based; ex-VP Yield Technology & Data Science at Micron and ex-Fab Director at IM Flash. Owns Boise + Clay manufacturing buildouts; testified before US Senate Energy Committee May 21 2024 on CHIPS-era US fab power demand. MIDS, UC Berkeley.
Manish Bhatia
Executive Vice President, Global Operations
At Micron since Oct 2017; reports to Sanjay Mehrotra. Scope includes fab and assembly/test manufacturing, smart manufacturing and AI. Named in the Jan 17 2026 PSMC Tongluo LOI announcement; sold $10.4M of MU stock 22 Jan 2026.
Fellow / Distinguished Member of Technical Staff, Technology Development (Boise)
Boise-based per his Micron-affiliated Google Scholar profile (9,759 citations) and ResearchGate. Gave IEDM 2025 Short Course SC 2.6 on emerging memory for AI/HPC (Dec 9 2025).
Sanjay Mehrotra
Chairman, President & CEO
Personally framed Boise R&D-HVM colocation as a time-to-market lever on the Q2 FY26 call (Mar 18 2026); inducted into the National Academy of Engineering in 2022; CEO since 2017.
+ 12 more identified · full list in export
1γ → 1δ inline defectivity at the Boise ramp gates HBM4 supply that's already pre-sold
Confidence: highThe Q2 FY26 prepared remarks state verbatim that 1γ is 'on track to become a majority of our DRAM bit mix by mid-calendar 2026' and that EUV adoption increases at 1δ with the latest-generation EUV tools. The Register reported that Micron has effectively pre-sold all HBM produced in 2026, and HBM4 base/core dies sit on the 1γ process — so any defect-density slip on Boise wafers translates directly into a customer commitment miss for NVIDIA Vera Rubin. Two independent yield/defect-engineering job families are actively open at Boise (RDA Process Engineer ID1, Product Yield Analytics Engineer JR65374), both explicitly calling for ML/data-science skills to find defects impacting yield. Confidence is high because the constraint is named on the earnings call and the operational response is visible in the hiring requisitions.
SIXSENSE ANGLE
No-code defect classifier trained per fab on Boise's own SEM / optical / die-level images, with engineers in the RDA org authoring inspection ROI/overlay logic — closes the days-to-classifier gap as 1γ feeds into HBM4 cores instead of waiting on a vendor's quarterly retraining cycle.
RDA team is being stood up against a 2027 first-wafer deadline — defect-detection tooling decisions are being made now
Confidence: highThe RDA HVM Process Engineer requisition states the role's goal is to 'run a team to reduce inline defectivity, coordinate with overseas manufacturing facilities for alignment, transfer technology to HVM and ensure RDA has inline visibility to defects to prevent excursion.' First fab output is targeted for 2H CY2027 (KIVI TV and Tom's Hardware reporting). That puts the inline-inspection toolchain selection inside a 12–18 month window with the engineering team being built today — exactly the window where vendor-locked, months-to-classifier tooling fails the schedule.
SIXSENSE ANGLE
Configurable inspection logic the RDA team authors and tunes themselves — engineers can change ROI definitions and classification rules without re-engaging the vendor, which is the operating lever during a process ramp where inspection criteria are still in flux.
Two parallel ramps: ID1 in Boise and PSMC Tongluo brownfield — same yield organization, doubled load
Confidence: mediumMicron will close the PSMC P5 acquisition in Q2 2026 and ramp DRAM there for 'meaningful wafer output' in H2 CY2027 — exactly when ID1 in Boise also reaches first output. EVP Global Ops Manish Bhatia owns both. Sustaining a same-day defect feedback loop across a greenfield US ramp and a Taiwan brownfield re-equip with the same yield organization is the kind of operational load where automation of classification (rather than headcount) is the only feasible answer.
SIXSENSE ANGLE
Closed-loop yield feedback — tying classifications back to specific tool / chamber / lot signals across two simultaneous ramps so the engineering team gets the feedback in days rather than the quarters that a vendor classifier retrain takes.
Short Course SC 2.6 — Emerging Memory Technologies for Next-Generation AI & HPC Applications
Fabio Pellizzer (Micron, Boise) · IEEE IEDM 2025, Hilton San Francisco Union Square
Open with Scott Gatzemeier, not Manish Bhatia. Bhatia owns global ops and is fielding inbound from every tool vendor in the world right now (he just signed the Tongluo LOI and sold $10M of stock the same week). Gatzemeier is the right peer for this conversation: he sits in Boise, he personally owns the ID1 + ID2 buildout, and his prior internal role was VP of Yield Technology and Data Science — which is literally the function buying a defect-classification platform. He also holds a Master of Information and Data Science from UC Berkeley, so the technical register is set high without having to translate down.
The hook is the gap between the Q2 FY26 narrative and the operational reality. On the March 18 call Mehrotra said colocation of R&D and HVM at Boise will 'speed up time to market for our leading-edge products' — and three days later the RDA Engineer DRAM and Product Yield Analytics requisitions are still open with ML/machine-vision skills called out as required. The substantive question is whether the in-house RDA team is standing up its classifier pipeline against KLA/AMAT inspection tools natively or whether they need an authoring layer on top — and what that decision looks like before ID1 first wafers in H2 2027.
Timing: now, not in three months. The $1.2B CHIPS reallocation from Clay to Boise (Nov 2025) plus the PSMC Tongluo closing in Q2 2026 pulls every yield-methods decision left by a quarter. By Q4 CY2026 the RDA team will have committed to its inline inspection toolchain for the ID1 ramp, and changing it after that costs headcount. The window to be the authoring layer rather than another vendor on the BOM is the next two quarters.
DRAFT EMAIL TO SCOTT GATZEMEIER
SubjectID1 RDA classifier authoring before H2 2027 first wafers
Scott — read your Senate Energy testimony from May 2024 and the more recent KIVI piece where you walked through the Boise build and the 3,500 direct hires plus the Lam / TEL / ASML / AMAT field-engineering load. The Q2 FY26 prepared remarks landed your colocation-speeds-time-to-market line cleanly, but the open RDA Engineer DRAM and Product Yield Analytics (JR65374) reqs read like the in-house ML-vision pipeline is still being staffed against the H2 2027 first-wafer date. The specific question I'd want your read on: when ID1 reaches inline inspection volume, is the RDA team planning to author and tune classification logic on the SEM/optical side directly, or sitting on the OEM-supplied classifier defaults until 1δ? Asking because the failure mode we keep seeing on greenfield 300mm DRAM ramps is the months-to-classifier cycle on the vendor side colliding with a process window that's still in flux — and your prior VP of Yield Technology & Data Science hat probably saw the same pattern at 1β. We work with fab engineering teams at the layer where yield/RDA engineers author their own per-fab classifiers and ROI logic on their own images, without going back to the tool vendor for a retrain. No 'AI dashboard' pitch — the question is just whether the bottleneck for Boise is going to be classifier authoring velocity or inspection tool throughput, because the answer changes what you'd want from a partner. Happy to send our writeup on how a 300mm DRAM team set this up during a node transition, or just trade notes — your call. Either way it's a useful conversation before the RDA toolchain freezes for ID1. [Your name]